This application claims the benefit of a Japanese Patent Application No.2004-308620 filed Oct. 22, 2004, in the Japanese Patent Office, the disclosure of which is hereby incorporated by reference.
1. Field of the Invention
The present invention generally relates to semiconductor devices and methods of producing the same, and more particularly to a semiconductor device having a semiconductor chip and a layer formed by spraying an aerosol particulate material, and a method of producing such a semiconductor device.
2. Description of the Related Art
The miniaturization and performance of electronic equipments have improved rapidly in various fields such as personal computers, portable telephones, Bluetooth (registered trademark) and other mobile equipments, aiming for an ubiquitous society, and there are demands to develop portable, wearable, mobile electronic equipments. In order to miniaturize such electronic equipments, there are demands to further improve the integration density of the packaging technology and the integration density of high-frequency circuits.
Particularly in the case of a large scale integrated circuit (LSI) chip, the integration, operation speed and functions have improved considerably, and LSI chips having approximately 3,000,000 gates within a single LSI chip and operating at a clock frequency of 500 MHz have been realized. In addition, the so-called system-on-chips have been developed, where the system-on-chip is mounted with a plurality of central processing units (CPUs), read only memories (ROMs), digital signal processors (DSPs) and the like.
In such an LSI chip using digital signals, a decoupling capacitor is provided in a periphery of the LSI chip in order to instantaneously flow an excessive current that is generated when a digital circuit of the LSI chip carries out a switching. The decoupling capacitor is provided between a power supply line and a ground line.
FIGS. 1 through 3 are cross sectional views showing examples of conventional circuit devices.
Conventionally, a decoupling capacitor 201 is arranged on a circuit board 203 on which an LSI chip 202 is mounted, as shown in FIG. 1. The decoupling capacitor 201 is electrically connected to the LSI chip 202 via wirings 204 and 205 of the circuit board 203.
In FIG. 2, the decoupling capacitor 201 is provided inside a multi-layer (or multi-level) circuit board 206 on which the LSI chip 202 is mounted.
In FIG. 3, the decoupling capacitor 201 is provided inside an interposer 210 that is provided between the LSI chip 202 and a circuit board 209. For example, a Japanese Laid-Open Patent Application No.2003-289128 proposes such an arrangement.
On the other hand, a circuit device having a semiconductor chip and a multi-layer wiring (or multi-level interconnection) board that are bonded without the use of bumps, where the decoupling capacitor is preformed within the multi-layer wiring board, has been proposed in a Japanese Laid-Open Patent Application 9-64236, for example.
However, in a case where a resin insulator layer made of an epoxy resin or the like is used for an interlayer insulator of the multi-layer wiring board, a resin that is mixed with ceramic powder is used for a capacitor dielectric layer of the decoupling capacitor due to the low heat resistance of the resin insulator layer. Since the dielectric constant of such a capacitor dielectric layer is approximately 10, it is impossible to form a decoupling capacitor having a sufficiently large electrostatic capacitance, and it is difficult to sufficiently bring out the functions of the decoupling capacitor.
In addition, in a case where sintered barium titanate is used for the capacitor dielectric layer, it is only possible to form one layer on a substrate having a high heat resistance of 800° C. to 1000° C. or higher, and there is a limit to the electrostatic capacitance that can be realized. Moreover, since a sintering process at a high temperature is required, the dimensions change after the sintering due to contraction or bowing, for example. For this reason, it is difficult to make the electrical connection and bonding with respect to the flat LSI chip having a high pin density, and there is a possibility of generating a defective connection or a disconnection.
Furthermore, problems similar to the above described problems encountered in the case of the decoupling capacitor are encountered when providing a damping resistor element and a terminating resistor element on the multi-layer wiring substrate.